1. Field of the Invention
The invention relates in general to a laterally double-diffused metal oxide semiconductor transistor (LDMOS) and method for fabricating the same, and more particularly to a laterally double-diffused metal oxide semiconductor transistor (LDMOS) comprising a double diffused source and a method for fabricating the same.
2. Description of the Related Art
When the size of the semiconductor is shrink, the channel between the source and drain is also reduced so as to speed up the operating rate of the whole transistor. However, if the channel of the metal oxide semiconductor transistor (MOS) is shortened, several problems, such as hot carrier effect, will happen.
In general, one of the resolution has been widely used is that adding a doped region at the junction of the channel and the drain/source, and doped concentration of this region is less than the source/drain. This is so called a lightly doped drain (LDD) structure.
Referring to FIGS. 1A˜1G, they are cross sectional view illustrating the conventional method for fabricating a laterally double-diffused metal oxide semiconductor transistor (LDMOS). The method for fabricating LDMOS includes following steps.
Firstly, a P type substrate 110 is provided, a N type first well 112 is formed on a part of the substrate 110, and a P type second well 114 is formed on another part of the substrate 110, as shown in FIG. 1A.
Next, several field oxide films (FOXs) are formed on a top surface of the substrate 110; a first FOX 122 and a second FOX 124 thereof are located in the first well 112, and a third FOX 126 and forth FOX 128 thereof are located in the second well 114 as shown in FIG. 1B.
Then, a gate 141 is formed on a part of the substrate 110 and a part of the second FOX 124 as shown in FIG. 1C.
Afterward, a drain is formed in the first well 112, and a lightly doped region is also formed in the second well 114 by self-alignment process, which includes following steps. A patterned photoresist layer 130 is formed by using a mask on the substrate 110, and the patterned photoresist layer 130 has an aperture 132 to expose the substrate 110 which is located between the first and third field oxide film 122 and 126, as shown in FIG. 1D. Then, ion implantation is performed by implanting the N type dopant into the substrate 110 to form the lightly doped region 162 of the source and the lightly doped region 152 of the drain, as shown in FIG. 1D.
After the patterned photoresist layer 130 is removed, the spacer 148 is formed on the side of the gate 141 to form the gate structure 140 as shown in FIG. 1E. Another patterned photoresist layer 134 of the same patterned is then formed on the substrate 110 with the same mask, and the ion implant process is performed as shown in FIG. 1F. N type dopant of high concentration is implanted into the substrate 110 which is masked by the gate structure 140 so as to form a heavily doped region 164 of the source and lightly doped region 154 of the drain. During the ion implant process, the lightly doped region 152 completely overlaps the heavily doped region 154 of the drain, but the lightly doped region 162 partially overlaps the heavily doped region 164 so that the lightly doped region 162 which is positioned beneath the spacer 148 projects from a laterally side of the heavily doped region 164 of the drain. Therefore, the structure of lightly doped drain (LDD) is formed by the self-alignment process.
After the patterned photoresist layer 134 is removed, P type dopant is implanted into the substrate 110 as a P type doped well 170, and a laterally double diffused metal oxide semiconductor conductor 100 is completed as shown in FIG. 1G.
However, hot carrier effect can't be solve by the structure of lightly doped drain, and the operating voltage of the transistor must be restricted to be under certain amount or else electrical breakdown will happen. When the operating voltage of the transistor is over the critical amount, the transverse electrical field increases and hot electrons are generated in the channel. Hot electrons having energy corrodes the drain and generated many electron and hole pairs, so that the amounts of carriers in the channel and near the drain is increased, as so called carrier multiplication. A part of generated electrons are usually attracted towards the drain to raise the current in the drain, and a part of electrons inject to the gate oxide layer. A part of generated holes flow to the substrate, as so called substrate current, and a part of holes are collected by the drain and enforce the NPN phenomenon that facilitates carrier multiplication and causes electrical breakdown finally.